The invention relates to buffer circuits, and more particularly, to buffer circuits with a reduced short circuit current and integrated circuits and ring oscillation circuits using the same.
CMOS buffer circuits are widely applied to drive devices connected to an output stage thereof. Generally, the power consumption of CMOS circuit is dynamic power consumption or short circuit power consumption. Dynamic power consumption is inevitable due to electric characteristics of CMOS buffer circuits, but short circuit power consumption results in wasted power. With advance of process technology, the smaller gate length of MOS transistors reduces the threshold voltage of the MOS transistors, such that short circuit current often occurs. To reduce short circuit power consumption, it is reasonable to focus to reduce short circuit current of buffers with high switching rate, such as clock buffers. The short circuit current of CMOS buffers also causes electronmagnetic interference (EMI). Thus, it is very important to reduce short circuit current for CMOS buffer circuits.
Many conventional methods have been disclosed to reduce short circuit current for buffer circuits. FIG. 1 shows a conventional CMOS buffer circuit 200 with reduced short circuit current. However, a short circuit current occurs not only in pre-driving stage 310 but also the output buffer driving stage 350. For example, when input (IN) is low in the beginning, the nodes 20 and 30 are at high, such that the transistors M36–M37 are turned on and transistor M38 is turned off. When the input (IN) goes high from low, the transistor M38 is turned on, the transistor M36 is turned off and the transistor M37 stays on until the voltage level at the node 20 goes low. Because gate terminals of the transistors M36 and M38 are connected, the transistors M36 and M38 are both turned on when the gate voltage crosses the middle range between the power voltage and the ground voltage, generating a short current through the transistors M36–M38. Further, as voltage levels at the nodes 20 and 30 go low from high, the PMOS transistors and NMOS transistors of inverters IN3 and IN4 are both turned on when the input terminals of cross the middle range between the power voltage and the ground voltage. Thus, there is a short circuit through the inverters IN3 and IN4. Similarly, when the input (IN) goes low from high, there is a short circuit current through the transistor M33–M35 and through the inverters IN3 and IN4.
FIG. 2 shows another conventional CMOS buffer circuit 500 with reduced short circuit current. When the input terminal 501 goes high from low, the voltage level at node 582 stays high but the voltage level at node 594 goes low from high, such that transistors M1 and M3 are turned on at the same time until the voltage level of node 582 is discharged to low, generating a short circuit through the transistors M1 and M3. Further, because the gate terminals of the transistors M5 and M6 are connected, one of the transistors M5 and M6 is always turned on, allowing a short circuit current through the transistors M5 and M6 when the input terminal 501 changes.
Namely, there is still a short circuit current through the output buffer driving stage 350 shown in FIG. 1 and the output buffer driving stage 550 shown in FIG. 2.